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data sheet 1994, 2000 the mark shows major revised points. mos integrated circuit 8-bit single-chip microcontrollers m pd78052,78053,78054,78055,78056,78058 description the m pd78052, 78053, 78054, 78055, 78056 and 78058 are m pd78054 subseries products of the 78k/0 series. a variety of peripheral functions such as an 8-bit resolution a/d converter, 8-bit resolution d/a converter, timer, serial interface, real-time output port and interrupt functions are included on chip. the m pd78p054 and 78p058, one-time prom or eprom products that can be operated in the same supply voltage range as the mask rom versions, and various development tools are also available. detailed function descriptions are provided in the following users manuals. be sure to read them before designing. m pd78054, 78054y subseries users manual: u11747e 78k/0 series users manual instructions: u12326e features ? high-capacity on-chip rom & ram item program data memory internal high- internal internal package part number memory (rom) speed ram buffer ram expansion ram m pd78052 16 kb 512 bytes 32 bytes none ? 80-pin plastic qfp (14 14 mm) m pd78053 24 kb 1024 bytes ? 80-pin plastic tqfp (fine pitch) m pd78054 32 kb (12 12 mm) m pd78055 40 kb m pd78056 48 kb m pd78058 60 kb 1024 bytes ? external memory expansion space: 64 kb ? minimum instruction execution time can be changed from high-speed (0.4 m s) to ultra-low-speed (122 m s) ? i/o ports: 69 (n-ch open drain: 4) ? 8-bit resolution a/d converter: 8 channels ? 8-bit resolution d/a converter: 2 channels ? serial interface: 3 channels ? timer: 5 channels ? supply voltage: v dd = 2.0 to 6.0 v applications cellular phones, pagers, printers, av equipment, air-conditioners, cameras, ppcs, fuzzy-logic home appliances, vending machines, etc. document no. u12327ej5v0ds00 (5th edition) date published february 2000 n cp(k) printed in japan the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
2 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 ordering information part number package m pd78052gc- -8bt 80-pin plastic qfp (14 14 mm) m pd78052gk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) m pd78053gc- -8bt 80-pin plastic qfp (14 14 mm) m pd78053gk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) m pd78054gc- -8bt 80-pin plastic qfp (14 14 mm) m pd78054gk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) m pd78055gc- -8bt 80-pin plastic qfp (14 14 mm) m pd78055gk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) m pd78056gc- -8bt 80-pin plastic qfp (14 14 mm) m pd78056gk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) m pd78058gc- -8bt 80-pin plastic qfp (14 14 mm) m pd78058gk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) remark indicates rom code suffix.
3 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 78k/0 series lineup the products in the 78k/0 series are listed below. the names enclosed in boxes are subseries names. 64-pin 64-pin 80-pin 80-pin 80-pin pd780034a pd780988 pd780034ay m m m 64-pin 64-pin pd780078 pd780078y m m emi-noise reduced version of the pd78054 m pd78018f with added uart and d/a converter and enhanced i/o m pd780024a with increased ram capacity m pd780024a with enhanced a/d converter m on-chip inverter controller and uart. emi-noise reduced. pd78044h pd780232 80-pin 80-pin pd78064 pd780841 pd78064b pd780308 100-pin 100-pin 100-pin pd780308y pd78064y 80-pin 78k/0 series for panel control. on-chip fip c/d. display output total: 53 lcd drive basic subseries for driving lcds, on-chip uart bus interface supported call id supported m m m m m m m 80-pin on-chip call id function, simple dtmf. emi-noise reduced. m pd78064 with enhanced sio, and increased rom, ram capacity. m emi-noise reduced version of the pd78064 m pd78083 pd78018f pd78018fy pd78014h m emi-noise reduced version of the pd78018f basic subseries for control on-chip uart, capable of operating at low voltage (1.8 v) m m m m 42/44-pin 64-pin 64-pin m a timer added to the pd780034a and serial i/o enhanced pd78018f with enhanced serial i/o m 80-pin m pd78054 with enhanced serial i/o 100-pin 100-pin products in mass production products under development y subseries products are compatible with i 2 c bus. 100-pin m pd78078y with enhanced serial i/o and limited functions pd78054 with timer added and enhanced external interface m rom-less version of the pd78078 m 100-pin emi-noise reduced version of the pd78078 m inverter control pd780228 100-pin m m pd780208 100-pin fip tm drive m pd78044f with enhanced i/o and fip c/d. display output total: 53 m pd78044h with enhanced i/o and fip c/d. display output total: 48 m pd780208 m pd78098b m pd78054 with iebus tm controller added. emi-noise reduced. m 100-pin pd780024a pd780024ay m m 80-pin 100-pin pd780958 pd780955 m m ultra-low power consumption. on-chip uart. 80-pin pd780973 m on-chip automobile meter controller/driver for industrial meter control meter control pd78044f 80-pin basic subseries for driving fip. display output total: 34 m pd78044f with added n-ch open drain i/o. display output total: 34 m 80-pin pd780701y on-chip d-can/iebus controller m 80-pin pd780833y on-chip controller compliant with j1850 (class 2) m pd780948 on-chip d-can controller m pd780065 m pd78054 pd78058f m m pd780058 m pd78070a pd78078 m m control pd78075b m pd78054y pd78058fy m m pd780058y m pd78070ay pd78078y pd780018ay m m m
4 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 the major functional differences among the subseries are listed below. function rom timer 8-bit 10-bit 8-bit serial interface i/o v dd min. external subseries name capacity 8-bit 16-bit watch wdt a/d a/d d/a value expansion control m pd78075b 32k to 40k 4 ch 1 ch 1 ch 1 ch 8 ch e 2 ch 3 ch (uart: 1 ch) 88 1.8 v ? m pd78078 48k to 60k m pd78070a ? 61 2.7 v m pd780058 24k to 60k 2 ch 3 ch (time division uart: 1 ch) 68 1.8 v m pd78058f 48k to 60k 3 ch (uart: 1 ch) 69 2.7 v m pd78054 16k to 60k 2.0 v m pd780065 40k to 48k ? 4 ch (uart: 1 ch) 60 2.7 v m pd780078 48k to 60k 2 ch ? 8 ch 3 ch (uart: 2 ch) 52 1.8 v m pd780034a 8k to 32k 1 ch 3 ch (uart: 1 ch) 51 m pd780024a 8 ch ? m pd78014h 2 ch 53 m pd78018f 8k to 60k m pd78083 8k to 16k ? ? 1 ch (uart: 1 ch) 33 ? inverter m pd780988 16k to 60k 3 ch note ? 1 ch ? 8 ch ? 3 ch (uart: 2 ch) 47 4.0 v ? control fip m pd780208 32k to 60k 2 ch 1 ch 1 ch 1 ch 8 ch ? ? 2 ch 74 2.7 v ? drive m pd780228 48k to 60k 3 ch ? ? 1 ch 72 4.5 v m pd780232 16k to 24k 4 ch 2 ch 40 m pd78044h 32k to 48k 2 ch 1 ch 1 ch 8 ch 1 ch 68 2.7 v m pd78044f 16k to 40k 2 ch lcd m pd780308 48k to 60k 2 ch 1 ch 1 ch 1 ch 8 ch ? ? 3 ch (time division uart: 1 ch) 57 2.0 v ? drive m pd78064b 32k 2 ch (uart: 1 ch) m pd78064 16k to 32k call id m pd780841 24k to 32k 2 ch ? 1 ch 1 ch 2 ch ? ? 2 ch (uart: 1 ch) 61 2.7 v ? supported m pd780948 60k 2 ch 2 ch 1 ch 1 ch 8 ch ? ? 3 ch (uart: 1 ch) 79 4.0 v ? m pd78098b 40k to 60k 1 ch 2 ch 69 2.7 v ? meter m pd780958 48k to 60k 4 ch 2 ch ? 1 ch ? ? ? 2 ch (uart: 1 ch) 69 2.2 v ? control m pd780955 40k 6 ch 1 ch 1 ch 2 ch (uart: 2 ch) 50 2.2 v m pd780973 24k to 32k 3 ch 1 ch 5 ch 2 ch (uart: 1 ch) 56 4.5 v note 16-bit timer: 2 channels 10-bit timer: 1 channel bus interface supported
5 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 overview of functions part number item m pd78052 m pd78053 m pd78054 m pd78055 m pd78056 m pd78058 internal rom 16 kb 24 kb 32 kb 40 kb 48 kb 60 kb memory high-speed ram 512 bytes 1024 bytes buffer ram 32 bytes expansion ram none 1024 bytes memory space 64 kb general-purpose registers 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution time on-chip minimum instruction execution time variable function when main system clock is selected 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s/12.8 m s (@ 5.0 mhz operation) when subsystem clock is selected 122 m s (@ 32.768 khz operation) instruction set 16-bit operation multiply/divide (8 bits 8 bits, 16 bits ? 8 bits) bit manipulation (set, reset, test, boolean operation) bcd correction, etc. i/o ports total: 69 cmos input : 0 2 cmos i/o : 63 n-ch open-drain i/o: 4 a/d converter 8-bit resolution 8 channels d/a converter 8-bit resolution 2 channels serial interface 3-wire serial i/o/sbi/2-wire serial i/o mode selectable: 1 channel 3-wire serial i/o mode (automatic data transmit/receive function for up to 32 bytes provided on chip): 1 channel 3-wire serial i/o/uart mode selectable: 1 channel timer 16-bit timer/event counter: 1 channel 8-bit timer/event counter: 2 channels watch timer: 1 channel watchdog timer: 1 channel timer outputs 3 (14-bit pwm output 1) clock output 19.5 khz, 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz, 2.5 mhz, 5.0 mhz (@ 5.0 mhz operation with main system clock) 32.768 khz (@ 32.768 khz operation with subsystem clock) buzzer output 1.2 khz, 2.4 khz, 4.9 khz, 9.8 khz (@ 5.0 mhz operation with main system clock) vectored maskable internal: 13, external: 7 interrupt non-maskable internal: 1 sources software 1 test inputs internal: 1, external: 1 supply voltage v dd = 2.0 to 6.0 v operating ambient temperature t a = e40 to +85 c package 80-pin plastic qfp (14 14 mm) 80-pin plastic tqfp (fine pitch) (12 12 mm)
6 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 contents 1. pin configuration (top view) ................................................................................................ 7 2. block diagram ............................................................................................................... ............ 9 3. pin functions ................................................................................................................ ............... 10 3.1 port pins ................................................................................................................... ................................. 10 3.2 non-port pins ............................................................................................................... ............................. 12 3.3 pin i/o circuits and recommended connection of unused pins ........................................................ 14 4. memory space ................................................................................................................. ............. 18 5. peripheral hardware function features ...................................................................... 19 5.1 ports ....................................................................................................................... .................................... 19 5.2 clock generator ............................................................................................................. ........................... 20 5.3 timer/event counter ......................................................................................................... ........................ 20 5.4 clock output controller ..................................................................................................... ...................... 23 5.5 buzzer output controller .................................................................................................... ..................... 23 5.6 a/d converter ............................................................................................................... ............................. 24 5.7 d/a converter .............................................................................................................. ............................. 25 5.8 serial interface ............................................................................................................ .............................. 25 5.9 real-time output port ....................................................................................................... ....................... 27 6. interrupt functions and test functions ........................................................................ 28 6.1 interrupt functions ......................................................................................................... .......................... 28 6.2 test functions .............................................................................................................. ............................. 32 7. external device expansion function ................................................................................ 33 8. standby function ............................................................................................................. ......... 33 9. reset function ............................................................................................................... ............ 33 10. instruction set ............................................................................................................. ............. 34 11. electrical specifications ................................................................................................... .. 36 12. characteristics curves (reference values) ................................................................ 64 13. package drawings ............................................................................................................ ........ 66 14. recommended soldering conditions ................................................................................ 68 appendix a. development tools ................................................................................................. 70 appendix b. related documents ................................................................................................ 7 3
7 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 1. pin configuration (top view) 80-pin plastic qfp (14 14 mm) m pd78052gc- -8bt, 78053gc- -8bt, 78054gc- -8bt, 78055gc- -8bt, m pd78056gc- -8bt, 78058gc- -8bt 80-pin plastic tqfp (fine pitch) (12 12 mm) m pd78052gk- -be9, 78053gk- -be9, 78054gk- -be9, 78055gk- -be9, m pd78056gk- -be9, 78058gk- -be9 p15/ani5 40 p64/rd p127/rtp7 p14/ani4 78 79 80 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 p13/ani3 p12/ani2 p11/ani1 p10/ani0 av ref0 av dd xt1/p07 xt2 ic x1 x2 v dd p06/intp6 p05/intp5 p04/intp4 p03/intp3 p02/intp2 p01/intp1/ti01 p00/intp0/ti00 reset p126/rtp6 p125/rtp5 p124/rtp4 p123/rtp3 p122/rtp2 p121/rtp1 p120/rtp0 p37 p36/buz p35/pcl p34/ti2 p33/ti1 p32/to2 p31/to1 p30/to0 p67/astb p66/wait p65/wr 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 p62 p63 p60 p61 p56/a14 p57/a15 v ss p53/a11 p54/a12 p55/a13 p52/a10 p50/a8 p51/a9 p46/ad6 p47/ad7 p44/ad4 p45/ad5 p42/ad2 p43/ad3 1 p16/ani6 p17/ani7 2 3 av ss 4 p130/ano0 5 p131/ano1 6 av ref1 7 p70/si2/r x d 8 p71/so2/t x d 9 p72/sck2/asck 10 p20/si1 11 p21/so1 12 p22/sck1 13 p23/stb 14 p24/busy 15 p25/si0/sb0 16 p26/so0/sb1 17 p27/sck0 18 19 20 p40/ad0 p41/ad1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 cautions 1. connect the ic (internally connected) pin directly to v ss . 2. connect the av dd pin to v dd . 3. connect the av ss pin to v ss .
8 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 a8 to a15: address bus ad0 to ad7: address/data bus ani0 to ani7: analog input ano0, ano1: analog output asck: asynchronous serial clock astb: address strobe av dd : analog power supply av ref0 , av ref1 : analog reference voltage av ss : analog ground busy: busy buz: buzzer clock ic: internally connected intp0 to intp6: external interrupt input p00 to p07: port0 p10 to p17: port1 p20 to p27: port2 p30 to p37: port3 p40 to p47: port4 p50 to p57: port5 p60 to p67: port6 p70 to p72: port7 p120 to p127: port12 p130, p131: port13 pcl: programmable clock rd: read strobe reset: reset rtp0 to rtp7: real-time output port r x d: receive data sb0, sb1: serial bus sck0 to sck2: serial clock si0 to si2: serial input so0 to so2: serial output stb: strobe ti00, ti01: timer input ti1, ti2: timer input to0 to to2: timer output t x d: transmit data v dd : power supply v ss : ground wait: wait wr: write strobe x1, x2: crystal (main system clock) xt1, xt2: crystal (subsystem clock)
9 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 2. block diagram remark the internal rom and ram capacity varies depending on the product. to0/p30 16-bit timer/ event counter ti00/intp0/p00 ti01/intp1/p01 to1/p31 8-bit timer/ event counter 1 ti1/p33 to2/p32 8-bit timer/ event counter 2 ti2/p34 watchdog timer watch timer si0/sb0/p25 serial interface 0 so0/sb1/p26 sck0/p27 si2/rxd/p70 serial interface 2 so2/txd/p71 sck2/asck/p72 av dd a/d converter av ss av ref0 ani0/p10 to ani7/p17 interrupt control intp0/p00 to intp6/p06 buzzer output buz/p36 clock output control pcl/p35 p00 port 0 p01 to p06 p07 port 1 p10 to p17 port 2 p25 to p27 port 3 p30 to p37 port 7 p70 to p72 p120 to p127 p130, p131 real-time output port rtp0/p120 to rtp7/p127 external access ad0/p40 to ad7/p47 astb/p67 reset x1 x2 xt1/p07 xt2 78k/0 cpu core rom ram system control v dd v ss ic a8/p50 to a15/p57 rd/p64 wr/p65 wait/p66 si1/p20 serial interface 1 so1/p21 sck1/p22 stb/p23 busy/p24 av ss d/a converter av ref1 ano0/p130, ano1/p131 port 4 p40 to p47 port 5 p50 to p57 port 6 p60 to p67 port 12 port 13
10 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 3. pin functions 3.1 port pins (1/2) pin name i/o function after alternate reset function p00 input port 0 input only input intp0/ti00 p01 i/o 8-bit i/o port input/output can be specified in 1-bit units. input intp1/ti01 p02 when used as an input port, a pull-up resistor can be intp2 p03 specified by means of software. intp3 p04 intp4 p05 intp5 p06 intp6 p07 note 1 input input only input xt1 p10 to p17 i/o port 1 input ani0 to ani7 8-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, a pull-up resistor can be specified by means of software note 2 . p20 i/o port 2 input si1 p21 8-bit i/o port. so1 p22 input/output can be specified in 1-bit units. sck1 p23 when used as an input port, a pull-up resistor can be specified by means stb p24 of software. busy p25 si0/sb0 p26 so0/sb1 p27 sck0 p30 i/o port 3 input to0 p31 8-bit i/o port. to1 p32 input/output can be specified in 1-bit units. to2 p33 when used as an input port, a pull-up resistor can be specified by means ti1 p34 of software. ti2 p35 pcl p36 buz p37 p40 to p47 i/o port 4 input ad0 to ad7 8-bit i/o port. input/output can be specified in 8-bit units. when used as an input port, a pull-up resistor can be specified by means of software. the test input flag (krif) is set to 1 by falling edge detection. notes 1. when using the p07/xt1 pin as an input port, set bit 6 (frc) of the processor clock control register (pcc) to 1. do not use the on-chip feedback resistor of the subsystem clock oscillator. 2. when using the p10/ani0 to p17/ani7 pins as a/d converter analog input pins, set port 1 to the input mode. at this time, pull-up resistors are automatically disconnected.
11 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 3.1 port pins (2/2) pin name i/o function after alternate reset function p50 to p57 i/o port 5 input a8 to a15 8-bit i/o port. leds can be driven directly. input/output can be specified in 1-bit units. when used as an input port, a pull-up resistor can be specified by means of software. p60 i/o port 6 n-ch open-drain i/o port. input p61 8-bit i/o port. an on-chip pull-up resistor can be p62 input/output can be specified in specified by the mask option. p63 1-bit units. leds can be driven directly. p64 when used as an input port, a input rd p65 pull-up resistor can be specified by wr p66 means of software. wait p67 astb p70 i/o input si2/rxd p71 so2/txd p72 sck2/asck p120 to p127 i/o port 12 input rtp0 to rtp7 8-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, a pull-up resistor can be specified by means of software. p130, p131 i/o port 13 input ano0, ano1 2-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, a pull-up resistor can be specified by means of software. port 7 3-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, a pull-up resistor can be specified by means of software.
12 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 3.2 non-port pins (1/2) pin name i/o function after alternate reset function intp0 input external interrupt request input for which the valid edge (rising edge, input p00/ti00 intp1 falling edge, or both rising and falling edges) can be specified. p01/ti01 intp2 p02 intp3 p03 intp4 p04 intp5 p05 intp6 p06 si0 input serial interface serial data input input p25/sb0 si1 p20 si2 p70/rxd so0 output serial interface serial data output input p26/sb1 so1 p21 so2 p71/txd sb0 i/o serial interface serial data input/output input p25/si0 sb1 p26/so0 sck0 i/o serial interface serial clock input/output input p27 sck1 p22 sck2 p72/asck stb output serial interface automatic transmit/receive strobe output input p23 busy input serial interface automatic transmit/receive busy input input p24 rxd input asynchronous serial interface serial data input input p70/si2 txd output asynchronous serial interface serial data output input p71/so2 asck input asynchronous serial interface serial clock input input p72/sck2 ti00 input external count clock input to the 16-bit timer (tm0) input p00/intp0 ti01 capture trigger signal input to the capture register (cr00) p01/intp1 ti1 external count clock input to the 8-bit timer (tm1) p33 ti2 external count clock input to the 8-bit timer (tm2) p34 to0 output 16-bit timer (tm0) output (also used for 14-bit pwm output) input p30 to1 8-bit timer (tm1) output p31 to2 8-bit timer (tm2) output p32 pcl output clock output (for trimming of main system clock and subsystem clock) input p35 buz output buzzer output input p36 rtp0 to rtp7 output real-time output port from which data is output in synchronization with input p120 to p127 a trigger ad0 to ad7 i/o lower address/data bus for expanding memory externally input p40 to p47 a8 to a15 output higher address bus for expanding memory externally input p50 to p57 rd output strobe signal output for reading from external memory input p64 wr strobe signal output for writing to external memory p65
13 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 3.2 non-port pins (2/2) pin name i/o function after alternate reset function wait input wait insertion at external memory access input p66 astb output strobe output that externally latches address information output to input p67 ports 4 and 5 to access external memory ani0 to ani7 input a/d converter analog input input p10 to p17 ano0, ano1 output d/a converter analog output input p130, p131 av ref0 input a/d converter reference voltage input av ref1 input d/a converter reference voltage input av dd a/d converter analog power supply. connect to v dd . av ss ground potential of a/d converter and d/a converter. connect to v ss . reset input system reset input x1 input connecting crystal resonator for main system clock oscillation x2 xt1 input connecting crystal resonator for subsystem clock oscillation input p07 xt2 v dd positive power supply v ss ground potential ic internally connected. connect directly to v ss .
14 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 3.3 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in table 3-1. for the input/output circuit configuration of each type, refer to figure 3-1 . table 3-1. types of pin input/output circuits (1/2) pin name input/output i/o recommended connection of unused pins circuit type p00/intp0/ti00 2 input connect to v ss . p01/intp1/ti01 8-a i/o input: independently connect to v ss via a resistor. p02/intp2 output: leave open. p03/intp3 p04/intp4 p05/intp5 p06/intp6 p07/xt1 16 input connect to v dd . p10/ani0 to p17/ani7 11 i/o input: independently connect to v dd or v ss via a resistor. p20/si1 8-a output: leave open. p21/so1 5-a p22/sck1 8-a p23/stb 5-a p24/busy 8-a p25/si0/sb0 10-a p26/so0/sb1 p27/sck0 p30/to0 5-a p31/to1 p32/to2 p33/ti1 8-a p34/ti2 p35/pcl 5-a p36/buz p37 p40/ad0 to p47/ad7 5-e input: independently connect to v dd via a resistor. output: leave open. p50/a8 to p57/a15 5-a input: independently connect to v dd or v ss via a resistor. output: leave open. p60 to p63 13-b input: independently connect to v dd via a resistor. output: leave open. p64/rd 5-a input: independently connect to v dd or v ss via a resistor. p65/wr output: leave open. p66/wait p67/astb
15 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 table 3-1. types of pin input/output circuits (2/2) pin name input/output i/o recommended connection of unused pins circuit type p70/si2/rxd 8-a i/o input: independently connect to v dd or v ss via a resistor. p71/so2/txd 5-a output: leave open. p72/sck2/asck 8-a p120/rtp0 to p127/rtp7 5-a i/o p130/ano0, p131/ano1 12-a i/o input: independently connect to v ss via a resistor. output: leave open note . reset 2 input xt2 16 leave open. av ref0 connect to v ss . av ref1 connect to v dd . av dd av ss connect to v ss . ic connect directly to v ss . note output a low level.
16 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 type 2 in type 8-a pull-up enable data output disable v p-ch n-ch p-ch in/out dd v dd type 10-a enable type 11 pull-up enable data output disable v p-ch n-ch p-ch in/out dd v dd type 5-a input enable type 5-e pull-up enable data output disable v p-ch n-ch p-ch in/out dd v dd schmitt-triggered input with hysteresis characteristics pull-up enable data output disable in/out n-ch v ref input dd (threshold voltage) v p-ch n-ch p-ch dd v p-ch + - comparator pull-up enable data output disable v p-ch n-ch p-ch in/out dd v dd open drain figure 3-1. pin input/output circuits (1/2)
17 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 type 12-a type 16 pull-up enable data output disable v p-ch n-ch p-ch in/out dd v dd n-ch input enable type 13-b data output disable n-ch p-ch in/out v dd v dd rd mask option middle voltage input buffer p-ch analog output voltage xt1 feed back cut-off xt2 p-ch figure 3-1. pin input/output circuits (2/2)
18 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 4. memory space figure 4-1 shows the m pd78052/78053/78054/78055/78056/78058 memory map. figure 4-1. memory map notes 1. m pd78058 only 2. if external device expansion functions are to be employed for the m pd78058, set the size of internal rom to 56 kb or below using the memory size switching register (ims). 3. the internal rom capacity and internal high-speed ram capacity differ depending on the product (see the following table). part number last address of internal rom first address of internal high-speed ram nnnnh mmmmh m pd78052 3fffh fd00h m pd78053 5fffh fb00h m pd78054 7fffh m pd78055 9fffh m pd78056 bfffh m pd78058 efffh special function registers (sfrs) 256 8 bits general-purpose registers 32 8 bits internal high-speed ram note 3 reserved internal buffer ram 32 8 bits reserved external memory internal rom note 3 data memory space program memory space ffffh ff00h feffh fee0h fedfh mmmmh mmmmh ?1 fae0h fadfh fac0h fabfh fa80h fa7fh nnnnh + 1 nnnnh 0000h reserved internal expanded ram 1024 8 bits reserved note 2 fa7fh f800h f7ffh f400h f3ffh f000h program area callf entry area program area callt table area vector table area nnnnh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h note 1
19 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 5. peripheral hardware function features 5.1 ports the following three types of i/o ports are available. cmos input (p00, p07): 2 cmos i/o (p01 to p06, port 1 to port 5, p64 to p67, port 7, port 12, port 13): 63 n-ch open-drain i/o (p60 to p63): 4 total: 69 table 5-1. port functions name pin name function port 0 p00, p07 input-only p01 to p06 i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. port 1 p10 to p17 i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. port 2 p20 to p27 i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. port 3 p30 to p37 i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. port 4 p40 to p47 i/o port. input/output can be specified in 8-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. the test flag (krif) is set to 1 by falling edge detection. port 5 p50 to p57 i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. leds can be driven directly. port 6 p60 to p63 n-ch open-drain i/o port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by the mask option. leds can be driven directly. p64 to p67 i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. port 7 p70 to p72 i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. port 12 p120 to p127 i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software. port 13 p130, p131 i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of software.
20 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 5.3 timer/event counter the m pd78052/78053/78054/78055/78056/78058 incorporate a 5-channel timer/event counter. 16-bit timer/event counter: 1 channel 8-bit timer/event counter: 2 channels watch timer: 1 channel watchdog timer: 1 channel table 5-2. operation of timer/event counter 16-bit timer/event counter 8-bit timer/event counter watch timer watchdog timer operation mode interval timer 1 channel 2 channels 1 channel 1 channel external event counter 1 channel 2 channels ? ? function timer output 1 output 2 outputs ? ? pwm output 1 output ? ? ? pulse amplitude measurement 2 inputs square wave output 1 output 2 outputs ? ? one-shot pulse output 1 output ? ? ? interrupt source 2 2 1 1 test input ? ? 1 input ? xt1/p07 xt2 x1 x2 f xt f xx subsystem clock oscillator watch timer, clock output function prescaler main system clock oscillator clock to peripheral hardware cpu clock (f cpu ) standby controller wait controller to intp0 sampling clock 2 f xx 2 2 f xx 2 3 f xx 2 4 f xx f xt 2 prescaler selector selector f x f x 2 stop scaler 2 1 5.2 clock generator two types of generators, a main system clock generator and a subsystem clock generator, are available. the minimum instruction execution time can also be changed. 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s/12.8 m s (@5.0 mhz operation with main system clock) 122 m s (@32.768 khz operation with subsystem clock) figure 5-1. clock generator block diagram
21 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 internal bus selector selector 16-bit timer register (tm0) clear output controller pwm pulse output controller 16-bit capture/ compare register internal bus intp1 inttm00 to0/p30 inttm01 intp0 ti01/p01/intp1 watch timer output 2f xx f xx f xx /2 2 f xx /2 ti00/p00/intp0 16-bit capture/ compare register (cr01) (cr00) edge detector match match selector internal bus 8-bit compare register (cr10) 8-bit timer register 1 (tm1) clear match selector output controller output controller inttm1 to2/p32 inttm2 to1/p31 clear match selector selector selector selector 8-bit compare register (cr20) 8-bit timer register 2 (tm2) internal bus f xx /2 to f xx /2 f x /2 9 11 ti1/p33 f xx /2 to f xx /2 f x /2 9 11 ti2/p34 figure 5-2. block diagram of 16-bit timer/event counter figure 5-3. block diagram of 8-bit timer/event counter
22 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 inttm3 intwt 5-bit counter prescaler selector selector selector selector f xx /2 f w f w f xt 7 2 f w 2 f w 2 f w 2 f w 2 f w 2 f w 2 f w 2 4 5 6 7 8 9 14 13 to 16-bit timer/ event counter controller 8-bit counter prescaler intwdt non-maskable interrupt request intwdt maskable interrupt request reset selector 4 5 6 7 8 9 11 2 3 f xx 2 f xx 2 f xx 2 f xx 2 f xx 2 f xx 2 f xx 2 f xx figure 5-4. watch timer block diagram figure 5-5. watchdog timer block diagram
23 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 selector synchronization circuit output controller pcl/p35 2 3 4 5 6 7 f xx /2 f xx /2 f xx /2 f xx /2 f xx /2 f xx /2 f xx /2 f xx f xt selector output controller buz/p36 9 10 11 f xx /2 f xx /2 f xx /2 5.4 clock output controller clocks with the following frequencies can be output as clock output. 19.5 khz/39.1 khz/78.1 khz/156 khz/313 khz/625 khz/1.25 mhz/2.5 mhz/5.0 mhz (@5.0 mhz operation with main system clock) 32.768 khz (@32.768 khz operation with subsystem clock) figure 5-6. block diagram of clock output controller 5.5 buzzer output controller clocks with the following frequencies can be output as buzzer output. 1.2 khz/2.4 khz/4.9 khz/9.8 khz (@5.0 mhz operation with main system clock) figure 5-7. block diagram of buzzer output controller
24 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 tap selector intad av dd intp3 internal bus av ref0 av ss a/d conversion result register (adcr) controller succesive approxmation register (sar) edge detector ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 ani5/p15 ani6/p16 ani7/p17 intp3/p03 selector sample & hold circuit voltage comparator series resistor string 5.6 a/d converter an a/d converter consisting of eight 8-bit resolution channels is incorporated. the following two a/d conversion operation start-up methods are available. hardware start software start figure 5-8. a/d converter block diagram
25 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 internal bus selector d/a conversion value set register n (dacsn) av ref1 av ss damm inttm x dacsn write anon d/a converter mode register 5.7 d/a converter a d/a converter consisting of two 8-bit resolution channels is available. the conversion method is the r-2r resistor ladder method. figure 5-9. d/a converter block diagram n = 0, 1 m = 4, 5 x = 1, 2 5.8 serial interface three clocked serial interface channels are incorporated. serial interface channel 0 serial interface channel 1 serial interface channel 2 table 5-3. types and functions of serial interface function serial interface channel 0 serial interface channel 1 serial interface channel 2 3-wire serial i/o mode (msb/lsb first switching (msb/lsb first switching (msb/lsb first switching possible) possible) possible) 3-wire serial i/o mode with auto- (msb/lsb first switching matic transmit/receive function possible) sbi (serial bus interface) mode (msb first) 2-wire serial i/o mode (msb first) asynchronous serial interface (on-chip dedicated baud (uart) mode rate generator)
26 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 busy/acknowledge output circuit output latch serial i/o shift register 0 (sio0) internal bus interrupt request signal generator serial clock counter bus release/command/ acknowledge detector serial clock controller selector selector selector si0/sb0/p25 so0/sb1/p26 sck0/p27 intcsi0 to2 f xx /2 to f xx /2 8 internal bus interrupt request signal generator handshake controller buffer ram serial clock controller selector serial counter serial i/o shift register 1 (sio1) automatic data transmit/ receive address pointer (adtp) automatic data transmit/receive interval specification register (adti) 5-bit counter intcsi1 f xx /2 to f xx /2 to2 8 si1/p20 so1/p21 stb/p23 busy/p24 sck1/p22 match figure 5-10. block diagram of serial interface channel 0 figure 5-11. block diagram of serial interface channel 1
27 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 rxd/si2/p70 txd/so2/p71 asck/sck2/p72 intser intsr/intcsi2 intst f xx to f xx /2 10 internal bus receive buffer register (rxb/sio2) direction controller receive shift register (rxs) receive controller direction controller transmit shift register (txs/sio2) transmit controller sck output controller baud rate generator internal bus p127 p120 output latch real-time output buffer register higher 4 bits (rtbh) real-time output buffer register lower 4 bits (rtbl) real-time output port mode register (rtpm) output trigger controller intp2 inttm1 inttm2 figure 5-12. block diagram of serial interface channel 2 5.9 real-time output port data set previously in the real-time output buffer register is transferred to the output latch by hardware concurrently with timer interrupt or external interrupt generation in order to output off-chip. this is a real-time output function. pins used to output off-chip are called real-time output ports. by using a real-time output port, a signal with no jitter can be output. this is most applicable to control of stepper motors, etc. figure 5-13. block diagram of real-time output port
28 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 6. interrupt functions and test functions 6.1 interrupt functions a total of 22 interrupt sources are provided, divided into the following three types. non-maskable: 1 maskable: 20 software: 1 the following table shows the interrupt source list. table 6-1. interrupt source list (1/2) default interrupt source internal/ vector basic interrupt type table configuration priority note 1 name trigger external address type note 2 non-maskable ? intwdt watchdog timer overflow internal 0004h (a) (with watchdog timer mode 1 selected) maskable 0 intwdt watchdog timer overflow (b) (with interval timer mode selected) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h (d) 3 intp2 000ah 4 intp3 000ch 5 intp4 000eh 6 intp5 0010h 7 intp6 0012h 8 intcsi0 end of serial interface channel 0 transfer internal 0014h (b) 9 intcsi1 end of serial interface channel 1 transfer 0016h 10 intser occurrence of serial interface channel 2 0018h uart reception error 11 intsr end of serial interface channel 2 uart 001ah reception intcsi2 end of serial interface channel 2 3-wire transfer 12 intst end of serial interface channel 2 uart 001ch transmission notes 1. default priority is the priority order when several maskable interrupt requests are generated at the same time. 0 is the highest and 18 is the lowest. 2. basic configuration types (a) to (e) correspond to (a) to (e) in figure 6-1.
29 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 table 6-1. interrupt source list (2/2) default interrupt source internal/ vector basic interrupt type table configuration priority note 1 name trigger external address type note 2 maskable 13 inttm3 reference time interval signal from internal 001eh (b) watch timer 14 inttm00 generation of match signal of 16-bit 0020h timer register and capture/compare register (cr00) 15 inttm01 generation of match signal of 16-bit 0022h timer register and capture/compare register (cr01) 16 inttm1 generation of match signal of 8-bit 0024h timer/event counter 1 17 inttm2 generation of match signal of 8-bit 0026h timer/event counter 2 18 intad end of a/d conversion 0028h software ? brk brk instruction execution ? 003eh (e) notes 1. default priority is the priority order when several maskable interrupt requests are generated at the same time. 0 is the highest and 18 is the lowest. 2. basic configuration types (a) to (e) correspond to (a) to (e) in figure 6-1.
30 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 figure 6-1. basic configuration of interrupt function (1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt (c) external maskable interrupt (intp0) internal bus priority controller vector table address generator standby release signal interrupt request mk internal bus ie pr isp if priority controller vector table address generator standby release signal interrupt request mk ie pr isp if priority controller vector table address generator sampling clock select register (scs) external interrupt mode register (intm0) edge detector sampling clock internal bus standby release signal interrupt request
31 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 figure 6-1. basic configuration of interrupt function (2/2) (d) external maskable interrupt (except intp0) (e) software interrupt if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag mk ie pr isp if priority controller vector table address generator external interrupt mode register (intm0, intm1) edge detector internal bus standby release signal interrupt request priority controller vector table address generator internal bus interrupt request
32 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 6.2 test functions table 6-2 shows the two test functions available. table 6-2. test input source list test input source internal/external name trigger intwt watch timer overflow internal intpt4 port 4 falling edge detection external figure 6-2. basic configuration of test function if: test input flag mk: test mask flag mk internal bus if standby release signal interrupt request
33 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 7. external device expansion function the external device expansion function is for the connection of external devices to areas other than the internal rom, ram and sfr. ports 4 to 6 are used for external device connection. 8. standby function the following two standby functions are available for further reduction of system current consumption. halt mode: in this mode, the cpu operating clock is stopped. the average current consumption can be reduced by intermittent operation by combining this mode with the normal operation mode. stop mode: in this mode, oscillation of the main system clock is stopped. all the operations performed on the main system clock are suspended, and only the subsystem clock is used, resulting in extremely small power consumption. figure 8-1. standby function note the current consumption can be reduced by stopping the main system clock. when the cpu is operating on the subsystem clock, set bit 7 (mcc) of the processor clock control register (pcc) to stop the main system clock. the stop instruction cannot be used. caution when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. 9. reset function the following two reset methods are available. external reset by reset signal input internal reset by watchdog timer runaway time detection main system clock operation stop mode (main system clock oscillation stopped) halt mode (clock supply to cpu halted, oscillation maintained) subsystem clock operation note halt mode note (clock supply to cpu halted, oscillation maintained) interrupt request interrupt request interrupt request halt instruction halt instruction stop instruction css=1 css=0
34 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 10. instruction set (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz 2nd operand 1st operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] [hl + b] [hl + c] $addr16 1 none a r add addc sub subc and or xor cmp mov mov mov mov mov mov mov mov ror xch xch xch xch xch xch xch rol add add add add add rorc addc addc addc addc addc rolc sub sub sub sub sub subc subc subc subc subc and and and and and or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp mov mov add addc sub subc and or xor cmp inc dec b, c sfr mov mov dbnz mov add addc sub subc and or xor cmp saddr mov dbnz inc dec !addr16 mov psw mov mov push pop [de] ror4 mov [hl] mov rol4 [hl + byte] [hl + b] [hl + c] mov x c mulu divuw note except r = a
35 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 (2) 16-bit instructions mov, xchw, addw, subw, cmpw, push, pop, incw, decw 2nd operand 1st operand ax rp sfrp saddrp !addr16 sp #word addw subw cmpw movw movw movw movw ax movw note movw movw movw movw movw rp note xchw sfrp movw saddrp movw !addr16 movw sp movw none incw, decw push, pop note only when rp = bc, de or hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr 2nd operand 1st operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none a.bit sfr.bit saddr.bit psw.bit [hl].bit cy mov1 mov1 mov1 mov1 mov1 bt bf btclr bt bf btclr bt bf btclr bt bf btclr bt bf btclr set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 not1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 (4) call instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz 2nd operand 1st operand ax !addr16 !addr11 [addr5] $addr16 basic instruction compound instruction br call br callf callt br, bc, bnc bz, bnz bt, bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop
36 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 11. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd e0.3 to +7.0 v av dd e0.3 to v dd + 0.3 v av ref0 e0.3 to v dd + 0.3 v av ref1 e0.3 to v dd + 0.3 v av ss e0.3 to +0.3 v input voltage v i1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, e0.3 to v dd + 0.3 v p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131, x1, x2, xt2, reset v i2 p60 to p63 n-ch open drain e0.3 to +16 v output voltage v o e0.3 to v dd + 0.3 v analog input voltage v an p10 to p17 analog input pin av ss e 0.3 to av ref0 + 0.3 v output i oh per pin e10 ma current, high total for p01 to p06, p30 to p37, p56, p57, e15 ma p60 to p67, p120 to p127 total for p10 to p17, p20 to p27, p40 to p47, e15 ma p50 to p55, p70 to p72, p130, p131 output i ol note per pin peak value 30 ma current, low rms value 15 ma total for p50 to p55 peak value 100 ma rms value 70 ma total for p56, p57, p60 to p63 peak value 100 ma rms value 70 ma total for p10 to p17, p20 to p27, peak value 50 ma p40 to p47, p70 to p72, p130, p131 rms value 20 ma total for p01 to p06, p30 to p37, peak value 50 ma p64 to p67, p120 to p127 rms value 20 ma operating ambient t a e40 to +85 c temperature storage t stg e65 to +150 c temperature note the rms value should be calculated as follows: [rms value] = [peak value] ? duty caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
37 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 main system clock oscillator characteristics (t a = C40 to +85 c, v dd = 2.0 to 6.0 v) resonator recommended circuit parameter conditions min. typ. max. unit ceramic oscillation v dd = oscillation voltage range 1.0 5.0 mhz resonator frequency (f x ) note 1 oscillation after v dd reaches oscillation 4 ms stabilization time note 2 voltage range min. crystal oscillation 1.0 5.0 mhz resonator frequency (f x ) note 1 oscillation v dd = 4.5 to 6.0 v 10 ms stabilization time note 2 30 external x1 input 1.0 5.0 mhz clock frequency (f x ) note 1 x1 input 85 500 ns high-/low-level width (t xh , t xl ) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. x1 x2 c2 c1 ic x1 x2 pd74hcu04 m x1 x2 c2 c1 ic r1
38 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 subsystem clock oscillator characteristics (t a = e40 to +85 c, v dd = 2.0 to 6.0 v) resonator recommended circuit parameter conditions min. typ. max. unit crystal oscillation 32 32.768 35 khz resonator frequency (f xt ) note 1 oscillation v dd = 4.5 to 6.0 v 1.2 2 s stabilization time note 2 10 external xt1 input 32 100 khz clock frequency (f xt ) note 1 xt1 input 5 15 m s high-/low-level width (t xth , t xtl ) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches oscillation voltage range min. cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. xt1 xt2 c4 c3 r2 ic xt1 xt2
39 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 recommended oscillator constant (1) m pd78052, 78053, 78054, 78055, 78056 main system clock: ceramic resonator (t a = e40 to +85 c) frequency recommended oscillation manufacturer product name circuit constant voltage range remarks (mhz) c1 (pf) c2 (pf) min. (v) max. (v) murata mfg. csa5.00mg 5.00 30 30 2.0 6.0 co., ltd. cst5.00mgw 5.00 on-chip on-chip 2.0 6.0 on-chip capacitor kyocera kbr-5.0msa 5.00 33 33 2.0 6.0 lead type corp. kbr-5.0mks 5.00 on-chip on-chip 2.0 6.0 on-chip capacitor, lead type kbr-5.0mws 5.00 on-chip on-chip 2.0 6.0 on-chip capacitor, lead type pbrc 5.00a 5.00 33 33 2.0 6.0 chip type tdk corp. ccr4.0mc3 4.00 on-chip on-chip 2.0 6.0 on-chip capacitor ccr5.0mc3 5.00 on-chip on-chip 2.0 6.0 on-chip capacitor main system clock: crystal resonator (t a = e10 to +70 c) frequency recommended oscillation manufacturer product name circuit constant voltage range (mhz) c3 (pf) c4 (pf) r2 (k w ) min. (v) max. (v) daishinku smd-49 3.579545 27 27 1.5 2.0 6.0 corp. subsystem clock: crystal resonator (t a = e10 to +70 c) frequency recommended oscillation manufacturer product name circuit constant voltage range (mhz) c1 (pf) c2 (pf) r1 (k w ) min. (v) max. (v) daishinku dt-38 32.768 27 20 330 2.0 6.0 corp. (1ta252e00) caution the oscillator constant and oscillation voltage range indicate conditions of stable oscillation. however, oscillation frequency precision is not guaranteed. for applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. for details, please contact directly the manufacturer of the resonator you will use.
40 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 (2) m pd78058 main system clock: ceramic resonator (t a = e40 to +85 c) frequency recommended oscillation manufacturer product name circuit constant voltage range remarks (mhz) c1 (pf) c2 (pf) min. (v) max. (v) kyocera pbrc4.19a 4.19 33 33 2.0 6.0 corp. pbrc4.19b 4.19 on-chip on-chip 2.0 6.0 on-chip capacitor kbr-4.19msa 4.19 33 33 2.0 6.0 kbr-4.19mks 4.19 on-chip on-chip 2.0 6.0 on-chip capacitor pbrc4.91a 4.91 33 33 2.0 6.0 pbrc4.91b 4.91 on-chip on-chip 2.0 6.0 on-chip capacitor kbr-4.91msa 4.91 33 33 2.0 6.0 kbr-4.91mks 4.91 on-chip on-chip 2.0 6.0 on-chip capacitor caution the oscillator constant and oscillation voltage range indicate conditions of stable oscillation. however, oscillation frequency precision is not guaranteed. for applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. for details, please contact directly the manufacturer of the resonator you will use. capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input c in f = 1 mhz 15 pf capacitance unmeasured pins returned to 0 v. i/o c io f = 1 mhz p01 to p06, p10 to p17, 15 pf capacitance unmeasured pins returned to 0 v. p20 to p27, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131 p60 to p63 20 pf remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
41 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 dc characteristics (t a = e40 to +85 c, v dd = 2.0 to 6.0 v) parameter symbol conditions min. typ. max. unit input voltage, v ih1 p10 to p17, p21, p23, p30 to p32, v dd = 2.7 to 6.0 v 0.7v dd v dd v high p35 to p37, p40 to p47, p50 to p57, p64 to p67, p71, p120 to p127, 0.8v dd v dd v p130, p131 v ih2 p00 to p06, p20, p22, p24 to p27, v dd = 2.7 to 6.0 v 0.8v dd v dd v p33, p34, p70, p72, reset 0.85v dd v dd v v ih3 p60 to p63 v dd = 2.7 to 6.0 v 0.7v dd 15 v (n-ch open drain) 0.8v dd 15 v v ih4 x1, x2 v dd = 2.7 to 6.0 v v dd e 0.5 v dd v v dd e 0.2 v dd v v ih5 xt1/p07, xt2 4.5 v v dd 6.0 v 0.8v dd v dd v 2.7 v v dd < 4.5 v 0.9v dd v dd v 2.0 v v dd < 2.7 v note 0.9v dd v dd v input voltage, v il1 p10 to p17, p21, p23, p30 to p32, v dd = 2.7 to 6.0 v 0 0.3v dd v low p35 to p37, p40 to p47, p50 to p57, p64 to p67, p71, p120 to p127, 0 0.2v dd v p130, p131 v il2 p00 to p06, p20, p22, p24 to p27, v dd = 2.7 to 6.0 v 0 0.2v dd v p33, p34, p70, p72, reset 0 0.15v dd v v il3 p60 to p63 4.5 v v dd 6.0 v 0 0.3v dd v 2.7 v v dd < 4.5 v 0 0.2v dd v 0 0.1v dd v v il4 x1, x2 v dd = 2.7 to 6.0 v 0 0.4 v 0 0.2 v v il5 xt1/p07, xt2 4.5 v v dd 6.0 v 0 0.2v dd v 2.7 v v dd < 4.5 v 0 0.1v dd v 2.0 v v dd < 2.7 v note 0 0.1v dd v output voltage, v oh v dd = 4.5 to 6.0 v, i oh = e1 ma v dd e 1.0 v high i oh = e100 m av dd e 0.5 v output voltage, v ol1 p50 to p57, p60 to p63 v dd = 4.5 to 6.0 v, 0.4 2.0 v low i ol = 15 ma p01 to p06, p10 to p17, p20 to p27, v dd = 4.5 to 6.0 v, 0.4 v p30 to p37, p40 to p47, p64 to p67, i ol = 1.6 ma p70 to p72, p120 to p127, p130, p131 v ol2 sb0, sb1, sck0 v dd = 4.5 to 6.0 v, 0.2v dd v open drain, pulled-up (r = 1 k w ) v ol3 i ol = 400 m a 0.5 v note when using the p07/x1 pin as p07, the inverse phase of p07 should be input to xt2. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
42 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 dc characteristics (t a = C40 to +85 c, v dd = 2.0 to 6.0 v) parameter symbol conditions min. typ. max. unit input leakage i lih1 v in = v dd p00 to p06, p10 to p17, 3 m a current, high p20 to p27, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p72, p120 to p127, p130, p131, reset i lih2 x1, x2, xt1/p07, xt2 20 m a i lih3 v in = 15 v p60 to p63 80 m a input leakage i lil1 v in = 0 v p00 to p06, p10 to p17, C3 m a current, low p20 to p27, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131, reset i lil2 x1, x2, xt1/p07, xt2 C20 m a i lil3 p60 to p63 C3 note 1 m a output leakage i loh v out = v dd 3 m a current, high output leakage i lol v out = 0 v C3 m a current, low mask option r 1 v in = 0 v, p60 to p63 20 40 90 k w pull- up resistor software r 2 v in = 0 v, p01 to p06, 4.5 v v dd 6.0 v 15 40 90 k w pull-up p10 to p17, p20 to p27, resistor note 2 p30 to p37, p40 to p47, p50 to p57, p64 to p67, 2.7 v v dd < 4.5 v 20 500 k w p70 to p72, p120 to p127, p130, p131 notes 1. when pull-up resistors are not connected to p60 to p63 (specifiable by the mask option), a low-level input leakage current of C200 m a (max.) flows only for 1.5 clocks (without wait) after a read instruction has been executed to port 6 (p6) or port mode register 6 (pm6). at times other than this 1.5-clock interval, a C3 m a (max.) current flows. 2. a software pull-up resistor can be used only in the range of v dd = 2.7 to 6.0 v. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
43 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 dc characteristics (t a = e40 to +85 c, v dd = 2.0 to 6.0 v) parameter symbol conditions min. typ. max. unit power supply i dd1 5.0 mhz crystal oscillation operating v dd = 5.0 v 10% note 5 412ma current note 1 mode (f xx = 2.5 mhz) note 2 v dd = 3.0 v 10% note 6 0.6 1.8 ma v dd = 2.2 v 10% note 6 0.35 1.05 ma 5.0 mhz crystal oscillation operating v dd = 5.0 v 10% note 5 6.5 19.5 ma mode (f xx = 5.0 mhz) note 3 v dd = 3.0 v 10% note 6 0.8 2.4 ma i dd2 5.0 mhz crystal oscillation halt v dd = 5.0 v 10% 1.4 4.2 ma mode (f xx = 2.5 mhz) note 2 v dd = 3.0 v 10% 0.5 1.5 ma v dd = 2.2 v 10% 280 840 m a 5.0 mhz crystal oscillation halt v dd = 5.0 v 10% 1.6 4.8 ma mode (f xx = 5.0 mhz) note 3 v dd = 3.0 v 10% 0.65 1.95 ma i dd3 32.768 khz crystal oscillation v dd = 5.0 v 10% 60 120 m a operating mode note 4 v dd = 3.0 v 10% 32 64 m a v dd = 2.2 v 10% 24 48 m a i dd4 32.768 khz crystal oscillation v dd = 5.0 v 10% 25 55 m a halt mode note 4 v dd = 3.0 v 10% 5 15 m a v dd = 2.2 v 10% 2.5 12.5 m a i dd5 xt1 = v dd v dd = 5.0 v 10% 1 30 m a stop mode v dd = 3.0 v 10% 0.5 10 m a when feedback resistor used v dd = 2.2 v 10% 0.3 10 m a i dd6 xt1 = v dd v dd = 5.0 v 10% 0.1 30 m a stop mode v dd = 3.0 v 10% 0.05 10 m a when feedback resistor not used v dd = 2.2 v 10% 0.05 10 m a notes 1. refers to the current flowing to the v dd and av dd pins. the current flowing to the a/d converter, d/a converter, and on-chip pull-up resistors are not included. 2. operation with main system clock f xx = f x /2 (when the oscillation mode selection register (osms) is set to 00h) 3. operation with main system clock f xx = f x (when osms is set to 01h) 4. when the main system clock operation is stopped. 5. high-speed mode operation (when the processor clock control register (pcc) is set to 00h). 6. low-speed mode operation (when pcc is set to 04h).
44 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 ac characteristics (1) basic operation (t a = e40 to +85 c, v dd = 2.0 to 6.0 v) parameter symbol conditions min. typ. max. unit cycle time t cy operating with main system clock v dd = 2.7 to 6.0 v 0.8 64 m s (minimum (f xx = 2.5 mhz) note 1 2.2 64 m s instruction operating with main system clock 4.5 v v dd 6.0 v 0.4 32 m s execution time) (f xx = 5.0 mhz) note 2 2.7 v v dd < 4.5 v 0.8 32 m s operating with subsystem clock 40 note 3 122 125 m s ti00, ti01, ti1, ti2 f ti v dd = 4.5 to 6.0 v 0 4 mhz input frequency 0 275 khz ti00 input high-/ t tih , 3.5 v v dd 6.0 v 2/f sam + 0.1 note 4 m s low-level width t til 2.7 v v dd < 3.5 v 2/f sam + 0.2 note 4 m s 2/f sam + 0.5 note 4 m s ti01 input high-/ t tih ,v dd = 4.5 to 6.0 v 10 m s low-level width t til 20 m s ti1, ti2 input high-/ t tih ,v dd = 4.5 to 6.0 v 100 ns low-level width t til 1.8 m s interrupt request t inth , intp0 3.5 v v dd 6.0 v 2/f sam + 0.1 note 4 m s input high-/ t intl 2.7 v v dd < 3.5 v 2/f sam + 0.2 note 4 m s low-level width 2/f sam + 0.5 note 4 m s intp1 to intp6, kr0 to kr7 v dd = 2.7 to 6.0 v 10 m s 20 m s reset t rsl v dd = 2.7 to 6.0 v 10 m s low-level width 20 m s notes 1. operation with main system clock f xx = f x /2 (when the oscillation mode selection register (osms) is set to 00h) 2. operation with main system clock f xx = f x (when osms is set to 01h) 3. value when an external clock is used. when a crystal resonator is used, it is 114 m s (min.). 4. selection of f sam = f xx /2 n , f xx /32, f xx /64, f xx /128 is possible with bits 0 and 1 (scs0, scs1) of the sampling clock selection register (scs) (when n= 0 to 4).
45 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 t cy vs. v dd (f xx = f x /2 main system clock operation) t cy vs. v dd (f xx = f x main system clock operation) 60 10 2.0 1.0 0.5 0.4 0 1234 56 supply voltage v dd [v] cycle time t cy [ s] guaranteed operation range 60 10 2.0 1.0 0.5 0.4 0 1234 56 supply voltage v dd [v] guaranteed operation range m cycle time t cy [ s] m
46 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 (2) read/write operation (a) when mcs = 1, pcc2 to pcc0 = 000b (t a = e40 to +85 c, v dd = 4.5 to 6.0 v) parameter symbol conditions min. max. unit astb high-level width t asth 0.85t cy e 50 ns address setup time t ads 0.85t cy e 50 ns address hold time t adh 50 ns data input time from address t add1 (2.85 + 2n)t cy e 80 ns t add2 (4 + 2n)t cy e 100 ns data input time from rd t rdd1 (2 + 2n)t cy e 100 ns t rdd2 (2.85 + 2n)t cy e 100 ns read data hold time t rdh 0ns rd low-level width t rdl1 (2 + 2n)t cy e 60 ns t rdl2 (2.85 + 2n)t cy e 60 ns input time from rd to wait t rdwt1 0.85t cy e 50 ns t rdwt2 2t cy e 60 ns input time from wr to wait t wrwt 2t cy e 60 ns wait low-level width t wtl (1.15 + 2n)t cy (2 + 2n)t cy ns write data setup time t wds (2.85 + 2n)t cy e 100 ns write data hold time t wdh 20 ns wr low-level width t wrl (2.85 + 2n)t cy e 60 ns delay time from astb to rd t astrd 25 ns delay time from astb to wr t astwr 0.85t cy + 20 ns delay time from rd - to astb - at t rdast 0.85t cy e 10 1.15t cy + 20 ns external fetch address hold time from rd - at t rdadh 0.85t cy e 50 1.15t cy + 50 ns external fetch write data output time from rd - t rdwd 40 ns write data output time from wr t wrwd 050ns address hold time from wr - t wradh 0.85t cy 1.15t cy + 40 ns delay time from wait - to rd - t wtrd 1.15t cy + 40 3.15t cy + 40 ns delay time from wait - to wr - t wtwr 1.15t cy + 30 3.15t cy + 30 ns remarks 1. mcs: bit 0 of the oscillation mode selection register (osms) 2. pcc2 to pcc0: bits 2 to 0 of the processor clock control register (pcc) 3. t cy = t cy /4 4. n indicates the number of waits.
47 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 (b) except when mcs = 1, pcc2 to pcc0 = 000b (t a = e40 to +85 c, v dd = 2.0 to 6.0 v) parameter symbol conditions min. max. unit astb high-level width t asth v dd = 2.7 to 6.0 v t cy e 80 ns t cy e 150 ns address setup time t ads v dd = 2.7 to 6.0 v t cy e 80 ns t cy e 150 ns address hold time t adh v dd = 2.7 to 6.0 v 0.4t cy e 10 ns 0.37t cy e 40 ns data input time from address t add1 v dd = 2.7 to 6.0 v (3 + 2n)t cy e 160 ns (3 + 2n)t cy e 320 ns t add2 v dd = 2.7 to 6.0 v (4 + 2n)t cy e 200 ns (4 + 2n)t cy e 300 ns data input time from rd t rdd1 v dd = 2.7 to 6.0 v (1.4 + 2n)t cy e 70 ns (1.37 + 2n)t cy e 120 ns t rdd2 v dd = 2.7 to 6.0 v (2.4 + 2n)t cy e 70 ns (2.37 + 2n)t cy e 120 ns read data hold time t rdh 0ns rd low-level width t rdl1 v dd = 2.7 to 6.0 v (1.4 + 2n)t cy e 20 ns (1.37 + 2n)t cy e 20 ns t rdl2 v dd = 2.7 to 6.0 v (2.4 + 2n)t cy e 20 ns (2.37 + 2n)t cy e 20 ns input time from rd to wait t rdwt1 v dd = 2.7 to 6.0 v t cy e 100 ns t cy e 200 ns t rdwt2 v dd = 2.7 to 6.0 v 2t cy e 100 ns 2t cy e 200 ns input time from wr to wait t wrwt v dd = 2.7 to 6.0 v 2t cy e 100 ns 2t cy e 200 ns wait low-level width t wtl (1 + 2n)t cy (2 + 2n)t cy ns write data setup time t wds v dd = 2.7 to 6.0 v (2.4 + 2n)t cy e 60 ns (2.37 + 2n)t cy e 100 ns write data hold time t wdh 20 ns wr low-level width t wrl v dd = 2.7 to 6.0 v (2.4 + 2n)t cy e 20 ns (2.37 + 2n)t cy e 20 ns delay time from astb to rd t astrd v dd = 2.7 to 6.0 v 0.4t cy e 30 ns 0.37t cy e 50 ns delay time from astb to wr t astwr v dd = 2.7 to 6.0 v 1.4t cy e 30 ns 1.37t cy e 50 ns remarks 1. mcs: bit 0 of the oscillation mode selection register (osms) 2. pcc2 to pcc0: bits 2 to 0 of the processor clock control register (pcc) 3. t cy = t cy /4 4. n indicates the number of waits.
48 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 (b) except when mcs = 1, pcc2 to pcc0 = 000b (t a = e40 to +85 c, v dd = 2.0 to 6.0 v) parameter symbol conditions min. max. unit delay time from rd - to astb - at t rdast t cy e 10 t cy + 20 ns external fetch address hold time from rd - at t rdadh t cy e 50 t cy + 50 ns external fetch write data output time from rd - t rdwd v dd = 2.7 to 6.0 v 0.4t cy e 20 ns 0.37t cy e 40 ns write data output time from wr t wrwd v dd = 2.7 to 6.0 v 0 60 ns 0 120 ns address hold time from wr - t wradh v dd = 2.7 to 6.0 v t cy t cy + 60 ns t cy t cy + 120 ns delay time from wait - to rd - t wtrd v dd = 2.7 to 6.0 v 0.6t cy + 180 2.6t cy + 180 ns 0.63t cy + 350 2.63t cy + 350 ns delay time from wait - to wr - t wtwr v dd = 2.7 to 6.0 v 0.6t cy + 120 2.6t cy + 120 ns 0.63t cy + 240 2.63t cy + 240 ns remarks 1. mcs: bit 0 of the oscillation mode selection register (osms) 2. pcc2 to pcc0: bits 2 to 0 of the processor clock control register (pcc) 3. t cy = t cy /4 4. n indicates the number of waits.
49 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 (3) serial interface (t a = e40 to +85 c, v dd = 2.0 to 6.0 v) (a) serial interface channel 0 (i) 3-wire serial i/o mode (sck0 ... internal clock output) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy1 4.5 v v dd 6.0 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 3200 ns sck0 high-/low-level t kh1 ,v dd = 4.5 to 6.0 v t kcy1 /2 e 50 ns width t kl1 t kcy1 /2 e 100 ns si0 setup time (to t sik1 4.5 v v dd 6.0 v 100 ns sck0 - ) 2.7 v v dd < 4.5 v 150 ns 300 ns si0 hold time (from t ksi1 400 ns sck0 - ) so0 output delay time t kso1 c = 100 pf note 300 ns from sck0 note c is the load capacitance of the so0 output line. (ii) 3-wire serial i/o mode (sck0 ... external clock input) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy2 4.5 v v dd 6.0 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 3200 ns sck0 high-/low-level t kh2 , 4.5 v v dd 6.0 v 400 ns width t kl2 2.7 v v dd < 4.5 v 800 ns 1600 ns si0 setup time t sik2 100 ns (to sck0 - ) si0 hold time t ksi2 400 ns (from sck0 - ) delay time from t kso2 c = 100 pf note 300 ns sck0 to so0 output sck0 rise, fall time t r2 , t f2 when using external device 160 ns expansion function when not using external device 1000 ns expansion function note c is the load capacitance of the so0 output line.
50 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 (iii) sbi mode (sck0 ... internal clock output) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy3 v dd = 4.5 to 6.0 v 800 ns 3200 ns sck0 high-/low-level t kh3 ,v dd = 4.5 to 6.0 v t kcy3 /2 e 50 ns width t kl3 t kcy3 /2 e 150 ns sb0, sb1 setup time t sik3 v dd = 4.5 to 6.0 v 100 ns (to sck0 - ) 300 ns sb0, sb1 hold time t ksi3 t kcy3 /2 ns (from sck0 - ) delay time from sck0 t kso3 r = 1 k w ,v dd = 4.5 to 6.0 v 0 250 ns to sb0, sb1 output c = 100 pf note 0 1000 ns sb0, sb1 from sck0 - t ksb t kcy3 ns sck0 from sb0, sb1 t sbk t kcy3 ns sb0, sb1 high-level t sbh t kcy3 ns width sb0, sb1 low-level t sbl t kcy3 ns width note r and c are the load resistance and load capacitance of the sck0, sb0, and sb1 output lines. (iv) sbi mode (sck0 ... external clock input) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy4 v dd = 4.5 to 6.0 v 800 ns 3200 ns sck0 high-/low-level t kh4 ,v dd = 4.5 to 6.0 v 400 ns width t kl4 1600 ns sb0, sb1 setup time t sik4 v dd = 4.5 to 6.0 v 100 ns (to sck0 - ) 300 ns sb0, sb1 hold time t ksi4 t kcy4 /2 ns (from sck0 - ) delay time from sck0 t kso4 r = 1 k w ,v dd = 4.5 to 6.0 v 0 300 ns to sb0, sb1 output c = 100 pf note 0 1000 ns sb0, sb1 from sck0 - t ksb t kcy4 ns sck0 from sb0, sb1 t sbk t kcy4 ns sb0, sb1 high-level t sbh t kcy4 ns width sb0, sb1 low-level t sbl t kcy4 ns width sck0 rise, fall time t r4 , t f4 when using external device 160 ns expansion function when not using external device 1000 ns expansion function note r and c are the load resistance and load capacitance of the sb0 and sb1 output lines.
51 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 (v) 2-wire serial i/o mode (sck0 ... internal clock output) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy5 r = 1 k w ,v dd = 2.7 to 6.0 v 1600 ns c = 100 pf note 3200 ns sck0 high-level width t kh5 v dd = 2.7 to 6.0 v t kcy5 /2 C 160 ns t kcy5 /2 C 190 ns sck0 low-level width t kl5 v dd = 4.5 to 6.0 v t kcy5 /2 C 50 ns t kcy5 /2 C 100 ns sb0, sb1 setup time t sik5 4.5 v v dd 6.0 v 300 ns (to sck0 - ) 2.7 v v dd < 4.5 v 350 ns 400 ns sb0, sb1 hold time t ksi5 600 ns (from sck0 - ) delay time from sck0 t kso5 0 300 ns to sb0, sb1 output note r and c are the load resistance and load capacitance of the sck0, sb0, and sb1 output lines. (vi) 2-wire serial i/o mode (sck0 ... internal clock input) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy6 v dd = 2.7 to 6.0 v 1600 ns 3200 ns sck0 high-level width t kh6 v dd = 2.7 to 6.0 v 650 ns 1300 ns sck0 low-level width t kl6 v dd = 2.7 to 6.0 v 800 ns 1600 ns sb0, sb1 setup time t sik6 100 ns (to sck0 - ) sb0, sb1 hold time t ksi6 t kcy6 /2 ns (from sck0 - ) delay time from sck0 t kso6 r = 1 k w ,v dd = 4.5 to 6.0 v 0 300 ns to sb0, sb1 output c = 100 pf note 0 500 ns sck0 rise, fall time t r6 , t f6 when using external device 160 ns expansion function when not using external device 1000 ns expansion function note r and c are the load resistance and load capacitance of the sb0 and sb1 output lines.
52 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 (b) serial interface channel 1 (i) 3-wire serial i/o mode (sck1 ... internal clock output) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy7 4.5 v v dd 6.0 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 3200 ns sck1 high-/low-level t kh7 ,v dd = 4.5 to 6.0 v t kcy7 /2 e 50 ns width t kl7 t kcy7 /2 e 100 ns si1 setup time t sik7 4.5 v v dd 6.0 v 100 ns (to sck1 - ) 2.7 v v dd < 4.5 v 150 ns 300 ns si1 hold time t ksi7 400 ns (from sck1 - ) delay time from sck1 t kso7 c = 100 pf note 300 ns to so1 output note c is the load capacitance of the so1 output line. (ii) 3-wire serial i/o mode (sck1 ... external clock input) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy8 4.5 v v dd 6.0 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 3200 ns sck1 high-/low-level t kh8 , 4.5 v v dd 6.0 v 400 ns width t kl8 2.7 v v dd < 4.5 v 800 ns 1600 ns si1 setup time t sik8 100 ns (to sck1 - ) si1 hold time t ksi8 400 ns (from sck1 - ) delay time from sck1 t kso8 c = 100 pf note 300 ns to so1 output sck1 rise, fall time t r8 , t f8 when using external device 160 ns expansion function when not using external device 1000 ns expansion function note c is the load capacitance of the so1 output line.
53 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 (iii) 3-wire serial i/o mode with automatic transmit/receive function (sck1 ... internal clock output) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy9 4.5 v v dd 6.0 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 3200 ns sck1 high-/low-level t kh9 ,v dd = 4.5 to 6.0 v t kcy9 /2 e 50 ns width t kl9 t kcy9 /2 e 100 ns si1 setup time t sik9 4.5 v v dd 6.0 v 100 ns (to sck1 - ) 2.7 v v dd < 4.5 v 150 ns 300 ns si1 hold time t ksi9 400 ns (from sck1 - ) so1 output delay time t kso9 c = 100 pf note 300 ns from sck1 stb - from sck1 - t sbd t kcy9 /2 e 100 t kcy9 /2 + 100 ns strobe signal t sbw v dd = 2.7 to 6.0 v t kcy9 e 30 t kcy9 + 30 ns high-level width t kcy9 e 60 t kcy9 + 60 ns busy signal setup time t bys 100 ns (to busy signal detection timing) busy signal hold time t byh 4.5 v v dd 6.0 v 100 ns (from busy signal 2.7 v v dd < 4.5 v 150 ns detection timing) 200 ns sck1 from busy t sps 2t kcy9 ns inactive note c is the load capacitance of the so1 output line. (iv) 3-wire serial i/o mode with automatic transmit/receive function (sck1 ... external clock input) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy10 4.5 v v dd 6.0 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 3200 ns sck1 high-/low-level t kh10 , 4.5 v v dd 6.0 v 400 ns width t kl10 2.7 v v dd < 4.5 v 800 ns 1600 ns si1 setup time t sik10 100 ns (to sck1 - ) si1 hold time t ksi10 400 ns (from sck1 - ) delay time from sck1 t kso10 c = 100 pf note 300 ns to so1 output sck1 rise, fall time t r10 , t f10 when using external device 160 ns expansion function when not using external device 1000 ns expansion function note c is the load capacitance of the so1 output line.
54 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 (c) serial interface channel 2 (i) 3-wire serial i/o mode (sck2 ... internal clock output) parameter symbol conditions min. typ. max. unit sck2 cycle time t kcy11 4.5 v v dd 6.0 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 3200 ns sck2 high-/low-level t kh11 ,v dd = 4.5 to 6.0 v t kcy7 /2 C 50 ns width t kl11 t kcy7 /2 C 100 ns si2 setup time t sik11 4.5 v v dd 6.0 v 100 ns (to sck2 - ) 2.7 v v dd < 4.5 v 150 ns 300 ns si2 hold time t ksi11 400 ns (from sck2 - ) delay time from sck2 t kso11 c = 100 pf note 300 ns to so2 output note c is the load capacitance of the so2 output line. (ii) 3-wire serial i/o mode (sck2 ... external clock input) parameter symbol conditions min. typ. max. unit sck2 cycle time t kcy12 4.5 v v dd 6.0 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 3200 ns sck2 high-/low-level t kh12 , 4.5 v v dd 6.0 v 400 ns width t kl12 2.7 v v dd < 4.5 v 800 ns 1600 ns si2 setup time t sik12 100 ns (to sck2 - ) si2 hold time t ks1i2 400 ns (from sck2 - ) delay time from sck2 t kso12 c = 100 pf note 300 ns to so2 output sck2 rise, fall time t r12 , when using external device 160 ns t f12 expansion function when not using external 1000 ns device expansion function note c is the load capacitance of the so2 output line.
55 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 (iii) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 4.5 v v dd 6.0 v 78125 bps 2.7 v v dd < 4.5 v 39063 bps 19531 bps (iv) uart mode (external clock input) parameter symbol conditions min. typ. max. unit asck cycle time t kcy13 4.5 v v dd 6.0 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 3200 ns asck high-/low-level t kh13 , 4.5 v v dd 6.0 v 400 ns width t kl13 2.7 v v dd < 4.5 v 800 ns 1600 ns transfer rate 4.5 v v dd 6.0 v 39063 bps 2.7 v v dd < 4.5 v 19531 bps 9766 bps asck rise, fall time t r13 ,v dd = 4.5 to 6.0 v, 1000 ns t f13 when not using external device expansion function. 160 ns
56 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 ac timing measurement points (excluding x1, xt1 input) clock timing ti timing 0.8v dd 0.2v dd 0.8v dd 0.2v dd point of measurement t xl t xh 1/f x v ih4 (min.) v il4 (max.) t xtl t xth 1/f xt v ih5 (min.) v il5 (max.) x1 input xt1 input 1/f ti t tih t til ti00, ti01, ti1, ti2
57 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 read/write operation external fetch (no wait): external fetch (wait insertion): t asth t adh t add1 hi-z t ads t rdadh t rdast t astrd t rdl1 t rdh a8 to a15 ad0 to ad7 astb rd t wtrd t wtl t rdwt1 wait t rdd1 higher 8-bit address operation code lower 8-bit address t asth t adh t add1 hi-z t ads t rdd1 t rdadh t rdast t astrd t rdl1 t rdh a8 to a15 ad0 to ad7 astb rd higher 8-bit address operation code lower 8-bit address
58 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 external data access (no wait): external data access (wait insertion): t astrd t asth t adh t add2 hi-z t ads t rdl2 a8 to a15 ad0 to ad7 astb rd t wds t wrl wr t rdh hi-z hi-z t wrwd t astwr t wradh higher 8-bit address write data read data lower 8-bit address t rdd2 t wdh t rdwd t astrd t asth t adh t add2 hi-z t ads t rdl2 a8 to a15 ad0 to ad7 astb rd t wds t wrl wr t rdh hi-z hi-z t wrwd t astwr t wradh higher 8-bit address write data read data lower 8-bit address t rdd2 t wdh t rdwt2 t wtl t wrwt t wtwr t wtl wait t wtrd t rdwd
59 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 serial transfer timing 3-wire serial i/o mode: sbi mode (bus release signal transfer): sbi mode (command signal transfer): t kcym t klm t khm sck0 to sck2 si0 to si2 so0 to so2 m = 1, 2, 7, 8, 11, 12 n = 2, 8, 12 t sikm t ksim t ksom input data output data t rn t fn t sik3, 4 t kcy3, 4 t kl3, 4 t kh3, 4 sck0 t sbl t sbh t ksb t sbk t ksi3, 4 t kso3, 4 sb0, sb1 t r4 t f4 t sik3, 4 t kcy3,4 t kl3, 4 t kh3, 4 sck0 t ksb t sbk t ksi3, 4 t kso3, 4 sb0, sb1 t r4 t f4
60 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 t kso5, 6 t sik5, 6 t kcy5, 6 t kl5, 6 t kh5, 6 sck0 t ksi5, 6 sb0, sb1 t f6 t r6 2-wire serial i/o mode: 3-wire serial i/o mode with automatic transmit/receive function: 3-wire serial i/o mode with automatic transmit/receive function (busy processing): note the signal is not actually driven low here; it is shown as such to indicate the timing. t bys sck1 t sps busy (active high) 789 note 10 note 10+n note 1 t byh t sbw t sbd t kcy9, 10 t kh9, 10 t ksi9, 10 t kso9, 10 t sik9, 10 d2 d1 d0 d7 d7 d2 d1 d0 so1 si1 sck1 stb t r10 t kl9, 10 t f10
61 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 uart mode (external clock input): t kcy13 t kh13 t kl13 t f13 t r13 asck a/d converter characteristics (t a = ?0 to +85 c, av dd = v dd = 2.0 to 6.0 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 8 8 bit overall error note 2.7 v av ref0 av dd 0.6 % 2.0 v av ref0 < 2.7 v 1.4 % conversion time t conv 19.1 200 m s sampling time t samp 12/f xx m s analog input voltage v ian av ss av ref0 v reference voltage av ref0 2.0 av dd v resistance between r airef0 4 14 k w av ref0 and av ss note excludes quantization error ( 1/2 lsb). this value is indicated as a ratio to the full-scale value. remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency d/a converter characteristics (t a = C40 to +85 c, v dd = 2.0 to 6.0 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 bit overall error r = 2 m w note 1 1.2 % r = 4 m w note 1 0.8 % r = 10 m w note 1 0.6 % settling time c = 30 pf note 1 4.5 v av ref1 6.0 v 10 m s 2.7 v av ref1 < 4.5 v 15 m s 2.0 v av ref1 < 2.7 v 20 m s output resistance r o dacs0, dacs1 = 55h note 2 10 k w analog reference voltage av ref1 2.0 v dd v resistance between r airef1 dacs0, dacs1 = 55h note 2 48 k w av ref1 and av ss notes 1. r and c are the d/a converter output pin load resistance and load capacitance, respectively. 2. value for one d/a converter channel remark dacs0 and dacs1: d/a conversion value setting registers 0 and 1
62 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 data memory stop mode low supply voltage data retention characteristics (t a = e40 to +85 c) parameter symbol conditions min. typ. max. unit data retention power v dddr 1.8 6.0 v supply voltage data retention power i dddr v dddr = 1.8 v 0.1 10 m a supply current when the subsystem clock is unused (xt1 = v dd ) and the feed-back resistor is disconnected release signal set time t srel 0 m s oscillation stabilization t wait release by reset 2 17 /f x ms wait time release by interrupt request note ms note selection of 2 12 /f xx and 2 14 /f xx to 2 17 /f xx is possible with bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time selection register (osts). remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency data retention timing (stop mode release by reset) t srel t wait v dd reset stop instruction execution stop mode data retension mode internal reset operation halt mode operating mode v dddr t srel t wait v dd stop instruction execution stop mode data retension mode halt mode operating mode standby release signal (interrupt request) v dddr data retention timing (standby release signal: stop mode release by interrupt request signal)
63 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 interrupt request input timing reset input timing t intl t inth intp0 to intp6 t rsl reset
64 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 12. characteristics curves (reference values) i dd vs. v dd (f x = f xx = 5.0 mhz) (t a = 25 c) pcc = 01h pcc = 00h pcc = 02h pcc = 03h pcc = 04h pcc = 30h halt (x1 oscillating, xt1 oscillating) pcc = b0h halt (x1 stopped, xt1 oscillating) 0 23456789 0.001 0.005 0.01 0.05 0.1 1.0 5.0 10.0 supply voltage v dd (v) supply current i dd (ma) 0.5
65 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 i dd vs. v dd (f x = 5.0 mhz, f xx = 2.5 mhz) (t a = 25 c) pcc = 00h pcc = 01h pcc = 02h pcc = 03h pcc = 30h halt (x1 oscillating, xt1 oscillating) pcc = b0h halt (x1 stopped, xt1 oscillating) 0 23456789 0.001 0.005 0.01 0.05 0.1 1.0 5.0 10.0 supply voltage v dd (v) supply current i dd (ma) pcc = 04h 0.5
66 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 80 pin plastic qfp (14 14) item millimeters inches note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. p80gc-65-8bt f 0.825 0.032 b 14.00?.20 0.551 +0.009 ?.008 s 1.70 max. 0.067 max. m 0.17 0.007 +0.001 ?.003 +0.03 ?.07 +0.009 ?.008 c 14.00?.20 0.551 +0.009 ?.008 a 17.20?.20 0.677?.008 g 0.825 0.032 h 0.32?.06 0.013 +0.002 ?.003 i 0.13 0.005 j 0.65 (t.p.) 0.026 (t.p.) k 1.60?.20 0.063?.008 l 0.80?.20 0.031 +0.009 ?.008 n 0.10 0.004 p 1.40?.10 0.055?.004 q 0.125?.075 0.005?.003 r3 3 +7 ? +7 ? d 17.20?.20 0.677?.008 41 60 40 61 21 80 20 1 m s q r k m l a b c d j h i f g p n detail of lead end 13. package drawings remark dimensions and materials of es product are the same as those of mass-production products.
67 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 20 1 s 80 pin plastic tqfp (fine pitch) (12x12) item millimeters i j 0.50 (t.p.) 0.10 a 14.00 0.20 b 12.00 0.20 c 12.00 0.20 d 14.00 0.20 f g 1.25 1.25 h 0.22 p80gk-50-be9-6 s 1.27 max. k 1.00 0.20 l 0.50 0.20 m 0.145 n 0.10 p 1.05 0.07 q 0.10 0.05 r5 5 +0.05 ?.04 +0.055 ?.045 j ns l k m detail of lead end 61 60 41 40 21 80 a b c d s qr g f p hi m note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. remark dimensions and materials of es product are the same as those of mass-production products.
68 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 14. recommended soldering conditions this product should be soldered and mounted under the following recommended conditions. for the details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact your nec sales represen- tative. table 14-1. surface mounting type soldering conditions (1/2) (1) m pd78052gc- -8bt: 80-pin plastic qfp (14 14 mm) m pd78053gc- -8bt: 80-pin plastic qfp (14 14 mm) m pd78054gc- -8bt: 80-pin plastic qfp (14 14 mm) m pd78055gc- -8bt: 80-pin plastic qfp (14 14 mm) m pd78056gc- -8bt: 80-pin plastic qfp (14 14 mm) m pd78058gc- -8bt: 80-pin plastic qfp (14 14 mm) soldering recommended method soldering conditions condition symbol infrared reflow ir35-00-2 vps vp15-00-2 wave soldering ws60-00-1 partial heating ? caution do not use different soldering methods together (except for partial heating). package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: twice max. package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: twice max. solder bath temperature: 260 c max., time: 10 seconds max., count: once, preheating temperature: 120 c max. (package surface temperature) pin temperature: 300 c max., time: 3 seconds max. (per pin row)
69 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 table 14-1. surface mounting type soldering conditions (2/2) (2) m pd78052gk- -be9: 80-pin plastic tqfp (12 12 mm) m pd78053gk- -be9: 80-pin plastic tqfp (12 12 mm) m pd78054gk- -be9: 80-pin plastic tqfp (12 12 mm) m pd78055gk- -be9: 80-pin plastic tqfp (12 12 mm) m pd78056gk- -be9: 80-pin plastic tqfp (12 12 mm) m pd78058gk- -be9: 80-pin plastic tqfp (12 12 mm) soldering recommended method soldering conditions condition symbol infrared reflow ir35-107-3 vps vp15-107-3 partial heating ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: three times max., exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: three times max., exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) pin temperature: 300 c max., time: 3 seconds max. (per pin row)
70 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 appendix a. development tools the following support tools are available for system development using the m pd78054 subseries. refer to (5) cautions on using development tools . (1) language processing software ra78k/0 assembler package common to 78k/0 series cc78k/0 c compiler package common to 78k/0 series df78054 m pd78054 subseries device file cc78k/0-l c compiler library source file common to 78k/0 series (2) prom writing tools pg-1500 prom programmer pa-78p054gc programmer adapter connected to a pg-1500 pa-78p054gk pa-78p054kk-t pg-1500 controller pg-1500 control program (3) debugging tools when using in-circuit emulator ie-78k0-ns ie-78k0-ns in-circuit emulator common to 78k/0 series ie-70000-mc-ps-b power supply unit for ie-78k0-ns ie-78k0-ns-pa note performance board to enhance and expand the functions of ie-78k0-ns ie-70000-98-if-c interface adapter when using pc-9800 series pc (except notebook type) as the host machine (c bus supported) ie-70000-cd-if-a pc card and interface cable when using notebook type pc as the host machine (pcmcia socket supported) ie-70000-pc-if-c interface adapter when using ibm pc/ata or compatible as the host machine ie-70000-pci-if adapter necessary when using pc including pci bus as the host machine ie-780308-ns-em1 emulation board common to m pd780308 subseries np-80gc emulation probe for 80-pin plastic qfp (gc-8bt type) np-80gc-tq np-80gk emulation probe for 80-pin plastic tqfp (gk-be9 type) ev-9200gc-80 conversion socket to connect the np-80gc and a target system board on which an 80-pin plastic qfp (gc-8bt type) can be mounted tgc-080sbp conversion socket to connect the np-80gc-tq and a target system board on which an 80-pin plastic qfp (gc-8bt type) can be mounted tgk-080sdw conversion adapter to connect the np-80gk and a target system board on which an 80-pin plastic tqfp (gk-be9 type) can be mounted id78k0-ns integrated debugger for ie-78k0-ns sm78k0 system simulator common to 78k/0 series df78054 device file for m pd78054 subseries note under development
71 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 when using in-circuit emulator ie-78001-r-a ie-78001-r-a in-circuit emulator common to 78k/0 series ie-70000-98-if-c interface adapter when using pc-9800 series pc (except notebook type) as the host machine (c bus supported) ie-70000-pc-if-c interface adapter when using ibm pc/at or compatible as the host machine (isa bus supported) ie-70000-pci-if adapter necessary when using pc including pci bus as the host machine ie-78000-r-sv3 interface adapter and cable when using ews as the host machine ie-780308-ns-em1 emulation board common to m pd780308 subseries ie-780308-r-em ie-78k0-r-ex1 emulation probe conversion board necessary when using ie-780308-ns-em1 on ie-78001-r-a ep-78230gc-r emulation probe for 80-pin plastic qfp (gc-8bt type) ep-78054gk-r emulation probe for 80-pin plastic tqfp (gk-be9 type) ev-9200gc-80 conversion socket to connect the ep-78230gc-r and a target system board on which an 80-pin plastic qfp (gc-8bt type) can be mounted tgk-080sdw conversion adapter to connect the ep-78054gk-r and a target system board on which an 80-pin plastic tqfp (gk-be9 type) can be mounted id78k0 integrated debugger for ie-78001-r-a sm78k0 system simulator common to 78k/0 series df78054 device file for m pd78054 subseries (4) real-time os rx78k/0 real-time os for 78k/0 series mx78k0 os for 78k/0 series
72 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 (5) cautions on using development tools the id78k0-ns, id78k0, and sm78k0 are used in combination with the df78054. the cc78k/0 and rx78k/0 are used in combination with the ra78k/0 and df78054. the np-80gc, np-80gc-tq, and np-80gk are products of naito densei machida mfg. co., ltd. (tel +81-44- 822-3813). consult an nec sales representative regarding purchase of these products. the tgk-080sdw and tgc-080sbp are products of tokyo eletech corporation. for further information, contact: daimaru kogyo ltd. tokyo electronics department (tel +81-3-3820-7112) osaka electronic department (tel +81-6-6244-6672) for third party development tools, refer to 78k/0 series selection guide (u11126e) . the host machines and operating systems suitable for each software are as follows. host machine pc ews [os] pc-9800 series [windowsa] hp9000 series 700a [hp-uxa] ibm pc/at compatibles sparcstationa [sunosa, solarisa] software [japanese/english windows] newsa (risc) [news-osa] ra78k/0 ? note ? cc78k/0 ? note ? pg-1500 controller ? note ? id78k0-ns ? ? id78k0 ?? sm78k0 ? ? rx78k/0 ? note ? mx78k0 ? note ? note dos-based software
73 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 appendix b. related documents documents related to devices document name document no. document no. (english) (japanese) m pd78054, 78054y subseries user?s manual u11747e u11747j m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet this document u12327j m pd78p054, 78p058 data sheet u10417e u10417j 78k/0 series user?s manual instructions u12326e u12326j 78k/0 series instruction set ? u10904j 78k/0 series instruction table ? u10903j m pd78054 subseries special function register table ? u10102j 78k/0 series application note basic (iii) u10182e u10182j floating point arithmetic programs iea-1289 u13482j documents related to development tools (user?s manuals) document name document no. document no. (english) (japanese) ra78k0 assembler package operation u11802e u11802j assembly language u11801e u11801j structured assembly language u11789e u11789j ra78k series structured assembler preprocessor eeu-1402 u12323j cc78k0 c compiler operation u11517e u11517j language u11518e u11518j cc78k0 c compiler application note programming know-how u13034e u13034j pg-1500 prom programmer u11940e u11940j pg-1500 controller pc-9800 series (ms-dosa) based eeu-1291 eeu-704 pg-1500 controller ibm pc series (pc dosa) based u10540e eeu-5008 ie-78k0-ns to be prepared to be prepared ie-78001-r-em to be prepared to be prepared ie-780308-ns-em1 to be prepared to be prepared ie-780308-r-em u11362e u11362j ep-78230 eeu-1515 eeu-985 ep-78054gk-r eeu-1468 eeu-932 sm78k0 system simulator windows based reference u10181e u10181j sm78k series system simulator external part user open u10092e u10092j interface specifications id78k0-ns integrated debugger windows based reference u12900e u12900j id78k0 integrated debugger ews based reference ? u11151j id78k0 integrated debugger pc based reference u11539e u11539j id78k0 integrated debugger windows based guide u11649e u11649j caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
74 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 documents related to embedded software (user?s manuals) document name document no. document no. (english) (japanese) 78k/0 series real-time os basics u11537e u11537j installation u11536e u11536j 78k/0 series os mx78k0 basics u12257e u12257j other related documents document name document no. document no. (english) (japanese) semiconductors selection guide products & packages (cd-rom) x13769x semiconductor device mounting technology manual c10535e c10535j quality grades on nec semiconductor devices c11531e c11531j nec semiconductor device reliability/quality control system c10983e c10983j guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e c11892j microcomputer product series guide ? u11416j caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
75 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 [memo]
76 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
77 m pd78052, 78053, 78054, 78055, 78056, 78058 data sheet u12327ej5v0ds00 nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j99.1
m pd78052, 78053, 78054, 78055, 78056, 78058 fip and iebus are trademarks of nec corporation. ms-dos and windows are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at and pc dos are trademarks of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. news and news-os are trademarks of sony corporation. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98.8 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative.

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